Activities

• KU060 Rev. 1 cards have been manufactured, deliveries in July 2020
• Next Step:
  • Get test IP ready testing is scheduled to start after Summer 2020 at LBNL.
• Beam time resources needed!
• Gen4 Backplane and FMC PCB-Fix Available

• For the duration of the test campaign no webex meetings will take place
• You can chat with Gary and Mike while they are streaming the test
• There will be an online beam-log (google docs)

• You are invited to join the test via Jitsi Meet by taking your web browser to this URL:
  • https://meet.jit.si/TAMUtest (try Chrome or Firefox)
  • Password: see (internal page) OR contact christian.fuchs (at) dependable.space

• KU060 Testing with Boeing (19th - 22nd):
• here are the hours in world time:
  • 6:00 to 14:00 US Pacific Time
  • 8:00 to 16:00 US Central Time
  • 15:00 to 23:00 Central European Summer Time (CEST)
  • 21:00 to 5:00 China Time Zone
  • 22:00 to 6:00 Japan Time Zone

• Next Step: Waiting to test functionally in September
• Test boards - ZCU102 with ZU9EG DUT - (6=NGC, 2=Sandia, 2=Aerospace, 3=Xilinx)
• Beam time resources needed:
  • USMDA 48h in 2 groups at Berekely
    • 3x8h during Aug. 5th-7th and 3x8h during Sep. 21st-23rd
  • The Berkeley Cyclotron failed, hence testing on Aug. 5th-7th was not possible.
  • New test date is scheduled for March 2021
  • New test date is scheduled for April 2021 at TAMU

• View the Live-Updated Beam-Log and Test plan (google docs)

• You are invited to join the test via Jitsi Meet by taking your web browser to this URL:
  • https://meet.jit.si/LBLtest (try Chrome or Firefox)
  • Password: see (internal page) OR contact christian.fuchs (at) dependable.space
  • You can use the text-chat function in this call and chat with Gary and Mike while they are streaming. Please make SURE to mute your microphone at all times and turn your camera off. Do not allow camera use.

• There will also be an interactive briefing held by Gary from 10:30 to 11:00 PST:
  • https://meet.jit.si/LBLbriefing
  • During this meeting you can ask question and suggest improvements Thursday through Saturday. Feel free to talk and chat, but remember also to keep your camera/video off.

• Zynq MPSoC/16nm Test Campaign (April 28-30th, May 1st and 2nd):
  • US Pacific Time:
    • 16:00 to 0:00/midnight on April 28-30th
    • 6:00 to 12:00/noon on May 1st and 2nd
  • CEST:
    • 1:00 to 9:00 April 29-30th and May 1st
    • 15:00 to 21:00 May 2nd and 3rd
  • China:
    • 7:00 to 15:00 April 29-30th and May 1st
    • 21:00 to 3:00 (next day) May 2nd and 3rd

Current Status:

• Next step: test functionally
• Test boards -ZCU102 with ZU9 DUT- (6=NGC, 2=Sandia, 2=Aerospace, 3=Xilinx)
• Beam time allocated, see below

Tested parts:

• ZCU102 with ZU9
• XCZU9EG-2FFVB1156I (I=industrial -40 to 100)
• Alternatives:
  • E=comm 0 to 100
  • Q=auto -40 to 125, doesn't exist
  • Mil part, not available yet

Currently allocated beam time:

• Beam time covered, NG paid for White Sands and MDA for 24h at LBNL
• USMDA 48h in 2 groups at Berekely – 3x8h during Aug 5th-7th plus 3x8h during Sep 22nd/27rd
  • Click here for updates.
  • includes preview test for KU060 DUT

Current Schedule:

• Next step: mount parts on eval boards, test functionally, and schedule heavy ion beam
• Acquire DUTs (12= Xilinx) done
  • DUT type: ZU9EG
  • Part Number: XCZU9EG-2FFVB1156I (I=industrial temp. range: -40 to 100 deg C)
    • pins: 34×34 BGA
    • package size: 35mm x 35mm
• Borrow test boards -ZCU102 with ZU9 DUT- (6=NGC, 2=Sandia, 2=Aero, 3=Xilinx) done
• Irradiate to several levels of displacement damage
  • 6 DUTs done, reactor neutrons at White Sands; levels = 5e13, 1e14, 2e14 (2), 3e14, and 5e14
    • 6 DUTs, 14 MeV generator neutrons, if needed
  • Cooling of activated DUTs at neutron facility done

Future:

• VLSI tests at room and high temp at Xilinx (postponed to after SEL tests)
• Re-work boards with irradiated DUTs (Whizz)
  • Possible socket: 3M Textool™ Open-Top BGA, Series 9325, full part# 21156-9325-00-2431, seeon 3M website
• De-lid and thin DUTs at JPL
• Functional tests still pass?
  • Ring Oscillator for speed
  • Config over JTAG, max speed
  • Processor benchmark tests (from Mitigation Working Group)
  • XADC and Sysmon for analog
  • IBERT for MGTs
  • IOBs
  • others?
• Add heating & temperature monitoring and power supply mods to test boards
• Perform heavy ion SEL test (at LBNL, beam time reserved: Aug 5-7, 2020)
• Publish results

Key References:

• 2018- D.S. Lee (Sandia) et al., “Single-Event Characterization of 16 nm FinFET Xilinx UltraScale+ Devices with Heavy Ion and Neutron Irradiation”, REDW paper
• 2018- Anderson (BYU) et al., “Neutron Radiation Beam Results for the Xilinx UltraScale+ MPSoC”, REDW paper
• 2016- Benedetto et al., “The Use of 14-MeV Monoenergetic Neutrons to Improve the Single Event Latch up Response of the Texas Instruments VSP1221”, REDW paper
  • key result, needed 2e14 to suppress SEL, reactor neutrons in elec spec at 1e14 but out at 2e14, okay with 14 MeV at 2e14 (raw or 1 MeV-equiv ?)
• 1999- Lacoe et al., “Neutron and proton irradiation for latchup suppression in a radiation-tolerant commercial submicron CMOS process”, IEEE-TNS paper
• 1979- Adams et al., “NEUTRON IRRADIATION FOR PREVENTION OF LATCH-UP IN MOS INTEGRATED CIRCUITS”, IAEA paper and IEEE-TNS paper

Current Status:

• Kintex-Ultrascale (20nm) in manufacturing
• Next Step: Get test IP ready testing is scheduled to start in Summer 2020 at LBNL.

Tested parts:

• space part: XQRKU060-CNA1509 (Xilinx-donated)
• commercial-equivalent part XCKU060-1FFVA1517I
• The KU060 DUT card accommodates either part

Target beam trips:

• Beam time resources needed!
• Berkeley, focused tests, usually 12-24 hours
  • ? [ Aerospace/USMDA?]
  • first preview beam time sharing together with US+ latchup demo
• Texas A&M, main data collection tests, usually 48-72 hours
  • spare time in August, from Raytheon available if this proposal is granted

Currently allocated beam time:

• Aerospace: 16 hours promised (TODO assert this is still the case)
• USMDA 48h in 2 groups at Berekely – 3x8h during Aug. 5th-7th plus 3x8h during Sep. 22nd/27rd
  • (mostly for US+, but also for KU060)
• Boeing: yes, assert how much and when (ideally TAMU)
• RAYTHEON: yes, assert how much and when (ideally TAMU)
• others: please get in touch and let us know!

Schedule:

• Aug/+? , ready for initial dynamic heavy ion tests plus config upsets and SEFIs as a by-product
  
• Jul/Aug.? , Fault Injection Campaign
• Jun. , Checkout DUT board and try out the designs in hardware
• Apr. 30, 2020, Kickoff builds of KU060 DUT card and another Gen4 backplane batch
• Jan. 5, 2018, Test preparation started, but lots of work left to do.
  • Port of test & FuncMon designs from V7 to KU for these primitives:
    1. IOBs (LVCMOS, LVDS, single-ended HSTL, others?) –[ Boeing ]–
    2. Clocking (PLL & MMCM) –[ Boeing ]–
    3. IOSERDES
    4. IODelay
    5. BRAMs/BRAM ECC/BRAM FIFO
  • Port of test & FuncMon designs from V5 to KU for these primitives:
    1. User Flip-flops (dynamic) –[ Boeing ]–
    2. DCI (on HP I/O's only)
    3. DSPs (static)
    4. DSPs (dynamic) –[ Boeing ]–
    5. MGTs –[ BYU ]–
       1. initial tests in 2019:
          1. SEAKR using their apparatus, Easter (Apr.18-22) 2019 at TAMU
          2. Boeing using VCU108 dev board, June 28, 2019 TAMU
          3. Boeing using VCU108 dev board, November, 2019 TAMU
  • Develop test & FuncMon designs from scratch for these primitives:
    1. PCIe –[ BYU, if SHREC sponsor ]–
    2. eMac –[ BYU, if SHREC sponsor ]–
    3. SysMon
    4. Others?
       
  • Develop test & FuncMon designs from scratch for other tests:
    1. Ring Oscillator –[ BYU ]–
    2. MicroBlaze, single-string and Xilinx TMR IP
    3. TMR –[SEAKR? + BYU + others?] –
    4. Others?

First DUT card built after the new Gen-4 motherboard, it plugs in as as DUT (device-under-test) or FuncMon and is available from XRTC partner Silicon Turnkey Solutions. The card may be populated with either the biggest monolithic device (980T) or for 200 more i/o pins (1100 total, not counting MGTs), the stacked-silicon 1140T; other footprint-compatible options are 485T or 690T devices. Industry-standard FMCs (FPGA mezzanine connectors) of the HPC (high pin count) type support a variety of custom and commercial granddaughter cards. Intended for use on the XRTC Gen4 backplane with full connectivity (among other things this will allow testing of flight designs), the on-board oscillators allow standalone use and checkout. For a quote and to place an order, contact Neil Sampson, nsampson@sts-usa.com , 602.770.9084 (cell) .

<hi #fff200>-[first DELIVERY, May 8, 2019]-</hi>
Update, 5-23-19: Now delivered boards with all four types of Virtex-7's!

First build successful! All features checked so far work, including MGTs (at 3.125 GHz); note: use MGT's with some extra care and thought as only one bank has D/C blocking (ie, A/C coupling) capacitors on RX pins.

1. Further dynamic and mitigation testing of the Virtex-7 (28nm family), untested primitives:
   • IODelay test ready to go (on “straddle” 980T DUT card + Gen2 motherboard)
   • Dynamic flip-flops
   • DSPs, both static and dynamic
   • MGTs, with and without protocol (Boeing may also share some recent results here soon)
     • <hi #99d9ea>Raytheon</hi>
       • UC-Davis, April 2-4, 2019
         • 485 MGTs (GTX) vs 980 MGTs (GTH)
           • DUTs: XQ7VX980T-1 RF1930I (previously irradiated 980 DUT only)
         • Apparatus: “Straddle” (aka “stripped down”) V7 DUT on Gen4 Backplane
           • FuncMon: serial USB FTDI cable (no BrainBox; worked OK)
           • ConfigMon: JTAG-version of BYU's JCM (SMAP problems encountered)
       • Northwestern, May 25, 2019
         • 980 MGTs (GTH) with TMRed protocol
           • DUTs: XQ7VX980T-1 RF1930I (new, unirradiated 980 DUT only)
         • Apparatus: same: re-worked “straddle” on Gen4 backplane
       • UC-Davis, June 26-28, 2019
         • 485 MGTs (GTX) vs 980 MGTs (GTH), TMRed protocol
           • DUTs: XQ7VX980T-1 RF1930I and XC7V485T (on new 'FULL' DUT boards)
         • Apparatus: “brand new “FULL” V7 Gen4 DUT boards on Gen4 Backplane
           • FuncMon: serial USB FTDI cable (no BrainBox; new improved version)
           • ConfigMon: SMAP-version of BYU's JCM
       • <hi #fff200> TAMU, Dec. 18-19, 2019 </hi>
         • Flight-like (i.e. complex) Design in Beam after Extensive Fault Injection
           • DUTs: XQ7VX980T-1 RF1930I (back to 'straddle' DUT boards)
         • Apparatus: mechanically supported & power-protected DUT boards on Gen4 Backplane
           • FuncMon: new, improved custom high speed serial (BrainBox no longer needed)
           • ConfigMon: SMAP-version of BYU's JCM
   • Test other types: 690T w/ heavy ions (BAE) or 1140T (this is SSI) w/ protons

Currently undergoing final review, the long awaited next-gen motherboard is expected to be formally released for manufacture soon (mid-Jan. 2018). The more we order, the cheaper the per-copy cost becomes. For ordering details, please contact Neil Sampson, nsampson@sts-usa.com , 602.770.9084 (cell) .
Volunteers needed for the Infrastructure Team which meets on Thursday mornings, 8am PST. The more eyes and brains scrutinizing the design, the more likely we get it right the first time. Next up: the KU060 DUT card. On hold: US/US+ Virtex DUT card.
-[MILESTONE: complete connection spec to STS on Friday, Jan 19]-
-[MILESTONE: complete schematic by STS on Wednesday, Jan 31]-
-[MILESTONE: complete layout by STS on Monday, Feb 12]-
-[HOLDING (for V7 & US DUT card compatibility check and trace cleanup): complete final review, release to manufacture on Friday, target May 28]-
-[MILESTONE: BUILD go-ahead, Sept.27]-
<hi #fff200>-[Now AVAILABLE: first deliveries were Dec 2018]-</hi>
———