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publications [2020/07/16 09:24]
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-===== XRTC Report Archive ===== +{{htmlmetatags>metatag-robots=()}} 
-----+===== XRTC Publications =====
  
 This page contains published XRTC documents, which were either presented at conferences, or are published by the consortium itself through the Xilinx Space Lounge. This page contains published XRTC documents, which were either presented at conferences, or are published by the consortium itself through the Xilinx Space Lounge.
-==== Xilinx Virtex-7 Military and Commercial ==== 
  
-* RADECS 2017 (Geneva) Data Workshop * associated documents: \\ +==== XRTC Workshop Proceedings ====
-  * <hi #fff200> [[https://ieeexplore.ieee.org/document/8696210|Published Paper]] </hi> +
-  * {{public:xrtc-00v7-btdc-00--preliminary.pdf | Manuscript (preprint)}} +
-  * {{public:swift-radecs2017-submission319.pdf | Original Submission}}  +
-  * {{public:swift-radecs2017-dw35-poster-latest.pdf | Poster (latest version)}} +
  
-** {{public:xrtc-v7-bt-dc-01-a-draft.pdf | Virtex-7 Architectural Features Report }} ** (DRAFT document) +[[https://xrtc.groups.et.byu.net/wiki/doku.php?id=meetings:2019_xrtc_workshop|XRTC Workshop 2019 Proceedings]]
  
-==== Xilinx Virtex-5 QV ====+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=1fe0f1c5-be32-4d9b-9da2-32a424e2815b&filename=XRTC_2018_Day_1.zip|XRTC Workshop 2018 Proceedings]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/V5QV-Static-SEU-Summary-Report.pdf|V5QV Static SEU Summary Report]]+[[https://www.xilinx.com/member/forms/download/xef.html?filename=XRTC_2017_Proceedings.zip|XRTC Workshop 2017 Proceedings]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/V5QV-ArchFeatures-SEU-Summary-Report.pdf|V5QV Arch. Features SEU Summary Report]]+[[https://www.xilinx.com/member/forms/download/xef.html?filename=XRTC_2017_Proceedings.zip|XRTC Workshop 2016 Proceedings]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/Dual-Node-JPL-pub1.pdf|Estimates of SEU Rates from Heavy Ions in Devices Exhibiting Dual-Node Susceptibility]]+[[https://www.xilinx.com/member/forms/download/xef.html?filename=XRTC_2017_Proceedings.zip|XRTC Workshop 2015 Proceedings]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/EDAC-final-IEEE-proof.pdf|Single-Event Upset (SEU) Results of Embedded Error Detect and Correct Enabled Block Random Access Memory (Block RAM) within the Xilinx XQR5VFX130]]+[[https://www.xilinx.com/member/forms/download/xef.html?filename=XRTC_2017_Proceedings.zip|XRTC Workshop 2014 Proceedings]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/MonrealRadecs2012_GRA.pdf|Upset Manifestations in Embedded Digital Signal Processors due to Single Event Effects]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=381224&filename=XRTC2013_Proceedings.zip|XRTC Workshop 2013 Proceedings]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/PID1149014_GRA.pdf|Single Event Effect Rate Analysis and Upset Characterization of FPGA Digital Signal Processors]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=381223&filename=XRTC2012-Proceedings.zip|XRTC Workshop 2012 Proceedings]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/14520-RATR-03.pdf|Radiation Test Report, Single Event Effects, Virtex-5QV Field Programmable Gate Array, Digital Signal Processors]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=381222&filename=XRTC2011-Proceedings.zip|XRTC Workshop 2011 Proceedings]]
  
-==== XILINX Virtex-4 QV ====+==== FPGA Characterization Reports ==== 
 +=== Xilinx Virtex-7 ===
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/V4-Static-SEU-Summary-Rept.pdf|Xilinx Virtex-4 QV Static SEU Characterization Summary]]+[[unpublished| The XRTC Virtex-7 Architectural Features Report]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/V4-DM.pdf|Xilinx Virtex-4 QV Dynamic and Mitigated Report]]+[[https://ieeexplore.ieee.org/document/8696210| Dynamic SEE testing of selected Architectural Features of Xilinx 28 nm Virtex-7 FPGAs (Paper)]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/4077291.pdf|Single Event Upsets in Xilinx Virtex-4 FPGA Devices]]+{{public:swift-radecs2017-dw35-poster-latest.pdf | Dynamic SEE Testing of Selected ArchitecturalFeatures of Xilinx 28 nm Virtex-7 FPGAs (Poster)}} 
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/Untitled.pdf|Static Upset Characteristics of the 90nm Virtex-4QV FPGAs]]+=== Xilinx Virtex-5 QV ===
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/04342559.pdf|Upset Characterization and Test Methodology of the PowerPC405 Hard-Core Processor Embedded in Xilinx Field Programmable Gate Arrays]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=d2c41e5d-2dfb-4e92-b806-95ec06442e94&filename=V5QV_CMT_Errata.pdf|V5QV Clock Management Tile Radiation Characterization Erratum]]
  
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=4e652d9f-002e-4212-89d4-e9ead9afb3f1&filename=V5QV-Static-SEU-Summary-Report-3.pdf|V5QV Static SEU Summary Report]]
  
-==== XILINX Virtex-II QV ====+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=005ac14f-a80d-4ccb-b101-78573d6df671&filename=V5QV-ArchFeatures-SEU-Summary-Report.pdf|V5QV Architecture Features SEU Summary Report]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/virtex2_0104-11.pdf|Xilinx Virtex-II QV Static SEU Summary Report]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=7526bed5-c9f5-40e7-b482-eff5a92741d9&filename=Dual-Node-JPL-pub1.pdf|Estimates of SEU Rates from Heavy Ions in Devices Exhibiting Dual-Node Susceptibility]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/Characterization-of-Upset-Induced-Degradation-of-Error-Mitigated-High-Speed-I-Os-Using-Fault-Injection-on-SRAM-Based-FPGAs2.pdf|Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I-O’s Using Fault Injection on SRAM Based FPGAs]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=67e384e4-8a0c-4e64-ab97-cdb91adf788c&filename=EDAC-final-IEEE-proof.pdf|SEU Results of Embedded Error Detect and Correct Enabled Block RAM within the Xilinx XQR5VFX130]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/Dynamic-testing-of-Xilinx-Virtex-II-field-programmable-gate-array-FPGA-input-output-blocks-IOBs1.pdf|Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input-output blocks (IOBs)]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=e4c76c48-755d-4b3c-818f-90590bc4e1d1&filename=MonrealRadecs2012_GRA.pdf|Upset Manifestations in Embedded Digital Signal Processors due to Single Event Effects]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/XilinxCompare.pdf|Comparison of Xilinx Virtex-II FPGA SEE Sensitivities to Protons and Heavy Ions]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=10c2e6b2-6cbe-4d7c-afb5-3c53055f0958&filename=PID1149014_GRA.pdf|Single Event Effect Rate Analysis and Upset Characterization of FPGA Digital Signal Processors]]
  
-**Other Xilinx Related Publications**+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=1fdafcfb-6197-434f-a8f9-018a909fe6a6&filename=14520-RATR-03.pdf|Radiation Test Report, Single Event Effects, Virtex-5QV Field Programmable Gate Array, Digital Signal Processors]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/211_george_p.pdf|Initial Single-Event Effects Testing and Mitigation in the Xilinx Virtex II-Pro FPGA]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=3be5fdcc-fe60-4b08-b8c9-b94982715688&filename=14520-RATR-01Rev-(002).pdf|Radiation Test Report, Single Event Effects, Virtex-5QV Field Programmable Gate Array, Multi-Gigabit Transceivers]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/01589225.pdf|Complex Upset Mitigation Applied to a Re-Configurable Embedded Processor]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=d0901a7a-59f8-4aca-a538-52ca8d2167cc&filename=06062534.pdf|Single-Event Characterization of Multi-Gigabit Transceivers (MGT) in Space-Grade Virtex- 5QV Field Programmable Gate Arrays (FPGA)]] 
 +=== XILINX Virtex-4 QV ===
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/GA-RADECS-paper_PA-GA-Reviewers-Final-Version-1_3_2011.pdf|Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=0f29c043-cad9-4b8c-b5a7-82b3edd64f05&filename=V4-Static-SEU-Summary-Rept.pdf|Xilinx Virtex-4 QV Static SEU Characterization Summary]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/JPL-Pub-09-35_Allen_Mitigation-Selection_100112-cfp.pdf|Mitigation Selection and Qualification Recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 Field Programmable Gate Arrays]]+[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=7d2c2001-8bb1-4469-998a-4723072741e6&filename=V4-DM.pdf|Xilinx Virtex-4 QV Dynamic and Mitigated Report]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=6b629bb0-62d0-446d-bd57-3ae618692e87&filename=4077291.pdf|Single Event Upsets in Xilinx Virtex-4 FPGA Devices]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=6c8113fe-0bde-4e68-b358-ea3b53622ee6&filename=Untitled.pdf|Static Upset Characteristics of the 90nm Virtex-4QV FPGAs]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=3f93be89-e929-43cd-a8d3-0da401b979d0&filename=04342559.pdf|Upset Characterization and Test Methodology of the PowerPC405 Hard-Core Processor Embedded in Xilinx Field Programmable Gate Arrays]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=381228&filename=xapp962-Single-Event-Upset-Mitigation-for-Xilinx-FPGA.pdf|XAPP962 - Single-Event Upset Mitigation for Xilinx FPGA Block Memories]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=381231&filename=xapp1004-Single-Event-Upset-Mitigation-Design-Flow.pdf|XAPP1004 - Single-Event Upset Mitigation Design Flow for Xilinx FPGA PowerPC Systems]] 
 +  * [[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=381235&filename=xapp1004.zip|Design Source]] 
 +=== XILINX Virtex-II QV === 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=8efff584-af4a-4b5d-999a-244a8d04ceab&filename=211_george_p.pdf|Initial Single-Event Effects Testing and Mitigation in the Xilinx Virtex II-Pro FPGA]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=172e8fe0-fc49-45be-9eb9-71755361a6b7&filename=virtex2_0104-11.pdf|Xilinx Virtex-II QV Static SEU Summary Report]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=98689877-74b1-4d34-b8e7-d0a3c0ddb014&filename=Characterization-of-Upset-Induced-Degradation-of-Error-Mitigated-High-Speed-I-Os-Using-Fault-Injection-on-SRAM-Based-FPGAs2.pdf|Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I-O’s Using Fault Injection on SRAM Based FPGAs]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=e6259426-306c-459d-9f64-8d57627d4ebe&filename=Dynamic-testing-of-Xilinx-Virtex-II-field-programmable-gate-array-FPGA-input-output-blocks-IOBs1.pdf|Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input-output blocks (IOBs)]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=6042b205-b33e-41be-9eb1-5a7d52cc7232&filename=XilinxCompare.pdf|Comparison of Xilinx Virtex-II FPGA SEE Sensitivities to Protons and Heavy Ions]] 
 + 
 +=== Other XRTC Publications === 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=b47a761a-307f-4d01-8981-9beeadb2c319&filename=01589225.pdf|Complex Upset Mitigation Applied to a Re-Configurable Embedded Processor]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=fc5e76b3-ec3b-4c61-84da-be31dd3bd9c7&filename=GA-RADECS-paper_PA-GA-Reviewers-Final-Version-1_3_2011.pdf|Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=87c913c5-e862-4e46-b2f5-3b63cd542725&filename=JPL-Pub-09-35_Allen_Mitigation-Selection_100112-cfp.pdf|Mitigation Selection and Qualification Recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 Field Programmable Gate Arrays]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=4723004c-cc67-4f50-b89a-1d11fc087567&filename=TMR-JPL-PUB.pdf|Analysis of Single-Event Upset Rates in Triple-Modular Redundancy Devices]] 
 + 
 +[[https://www.xilinx.com/member/forms/download/presentation-download.html?cid=771edebc-4ab2-4b36-87d3-0e0f07ad733c&filename=17v16_sefi.pdf|Heavy Ion SEE Testing of the Xilinx XQR17V16 Configuration PROM]]
  
-[[http://parts.jpl.nasa.gov/wp-content/uploads/TMR-JPL-PUB.pdf|Analysis of Single-Event Upset Rates in Triple-Modular Redundancy Devices]] 
  • publications.1594891453.txt.gz
  • Last modified: 2020/07/16 09:24
  • by christian