metatag-robots=()
XRTC Publications
This page contains published XRTC documents, which were either presented at conferences, or are published by the consortium itself through the Xilinx Space Lounge.
XRTC Workshop Proceedings
XRTC Workshop 2019 Proceedings
XRTC Workshop 2018 Proceedings
XRTC Workshop 2017 Proceedings
XRTC Workshop 2016 Proceedings
XRTC Workshop 2015 Proceedings
XRTC Workshop 2014 Proceedings
XRTC Workshop 2013 Proceedings
FPGA Characterization Reports
Xilinx Virtex-7
The XRTC Virtex-7 Architectural Features Report
Dynamic SEE testing of selected Architectural Features of Xilinx 28 nm Virtex-7 FPGAs (Paper)
Dynamic SEE Testing of Selected ArchitecturalFeatures of Xilinx 28 nm Virtex-7 FPGAs (Poster)
Xilinx Virtex-5 QV
V5QV Clock Management Tile Radiation Characterization Erratum
V5QV Static SEU Summary Report
V5QV Architecture Features SEU Summary Report
Estimates of SEU Rates from Heavy Ions in Devices Exhibiting Dual-Node Susceptibility
SEU Results of Embedded Error Detect and Correct Enabled Block RAM within the Xilinx XQR5VFX130
Upset Manifestations in Embedded Digital Signal Processors due to Single Event Effects
Single Event Effect Rate Analysis and Upset Characterization of FPGA Digital Signal Processors
XILINX Virtex-4 QV
Xilinx Virtex-4 QV Static SEU Characterization Summary
Xilinx Virtex-4 QV Dynamic and Mitigated Report
Single Event Upsets in Xilinx Virtex-4 FPGA Devices
Static Upset Characteristics of the 90nm Virtex-4QV FPGAs
XAPP962 - Single-Event Upset Mitigation for Xilinx FPGA Block Memories
XAPP1004 - Single-Event Upset Mitigation Design Flow for Xilinx FPGA PowerPC Systems
XILINX Virtex-II QV
Initial Single-Event Effects Testing and Mitigation in the Xilinx Virtex II-Pro FPGA
Xilinx Virtex-II QV Static SEU Summary Report
Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input-output blocks (IOBs)
Comparison of Xilinx Virtex-II FPGA SEE Sensitivities to Protons and Heavy Ions