This page contains published XRTC documents, which were either presented at conferences, or are published by the consortium itself through the Xilinx Space Lounge.

* RADECS 2017 (Geneva) Data Workshop * associated documents:

• <hi #fff200> Published Paper </hi>
• Manuscript (preprint)
• Original Submission
• Poster (latest version)

Virtex-7 Architectural Features Report (Early DRAFT)

V5QV Static SEU Summary Report

V5QV Arch. Features SEU Summary Report

Estimates of SEU Rates from Heavy Ions in Devices Exhibiting Dual-Node Susceptibility

Single-Event Upset (SEU) Results of Embedded Error Detect and Correct Enabled Block Random Access Memory (Block RAM) within the Xilinx XQR5VFX130

Upset Manifestations in Embedded Digital Signal Processors due to Single Event Effects

Single Event Effect Rate Analysis and Upset Characterization of FPGA Digital Signal Processors

Radiation Test Report, Single Event Effects, Virtex-5QV Field Programmable Gate Array, Digital Signal Processors

Xilinx Virtex-4 QV Static SEU Characterization Summary

Xilinx Virtex-4 QV Dynamic and Mitigated Report

Single Event Upsets in Xilinx Virtex-4 FPGA Devices

Static Upset Characteristics of the 90nm Virtex-4QV FPGAs

Upset Characterization and Test Methodology of the PowerPC405 Hard-Core Processor Embedded in Xilinx Field Programmable Gate Arrays

Xilinx Virtex-II QV Static SEU Summary Report

Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I-O’s Using Fault Injection on SRAM Based FPGAs

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input-output blocks (IOBs)

Comparison of Xilinx Virtex-II FPGA SEE Sensitivities to Protons and Heavy Ions

Initial Single-Event Effects Testing and Mitigation in the Xilinx Virtex II-Pro FPGA

Complex Upset Mitigation Applied to a Re-Configurable Embedded Processor

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

Mitigation Selection and Qualification Recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 Field Programmable Gate Arrays

Analysis of Single-Event Upset Rates in Triple-Modular Redundancy Devices